The production of advanced silicon-based micro-electro-mechanical systems, MEMS, requires the integration of moving mechanical parts and controlling, sensing or interfacing integrated circuits, and sometimes high-voltage integrated circuits capable actuating the mechanical parts.
The processes used to produce advanced MEMS from silicon-based structural materials typically require a high-temperature stress-relief step to reduce the mechanical stress of silicon-based structural material and allow its proper machining and mechanical release of the moving parts. This high-temperature stress-relief imposes the integrated circuit to be fabricated after the high surface topology mechanical parts of these advanced MEMS. This is an undesirable combination since advanced integrated circuits require very fine lithography to be performed using short depth-of-focus equipment. The high surface topology imposed by the mechanical parts is then to be eliminated by proper chemical-mechanical polishing (CMP), or other means, to allow the integrated circuit to be fabricated. The high-temperature stress-relief restriction, the extra cost associated with CMP planarization, and the need to fabricate the integrated circuit after the mechanical parts are significant restrictions on existing processes.
The integration of moving mechanical parts, of controlling, sensing or interfacing integrated circuits and, sometimes, of high-voltage integrated circuits capable of powerful actuation of the mechanical parts has been so far limited by the high-temperature stress-relief of polysilicon at temperatures exceeding 1000° C.
Examples of Restrictive High-Temperature Stress-Relief Processes of Polysilicon at Temperatures Exceeding 1000° C.
Analog Devices' Modular MEMS Process
A first well known example of a restrictive high-temperature stress-relief process is Analog Devices' Modular-MEMS process involving the integration of a 6 μm thick moving polysilicon structural material and a 5V 0.8 μm CMOS process for the control, sensing and interfacing functions. An example of this process is described in the following reference: Moorthi Palaniapan, Roger T. Howe, John Yasaitis, “Integrated Surface-Micromachined Z-axis Frame Microgyroscope”, International Electron Device Meeting 2002, San Francisco, Dec. 8–11, 2002, Session 8: Detectors, sensors and displays—Recent advances in inertial and biological MEMs. This reference shows that Analog Devices' Modular MEMS process uses a high-temperature stress-relief of a 6 μm thick moving polysilicon structural layer forming the mechanical parts. Following this high-temperature stress-relief a thick selective epitaxial silicon layer is epitaxially grown and used as substrate for the integrated circuit fabricated after a chemical-mechanical polishing, CMP, is performed as to achieve a smooth surface. The epitaxial silicon deposition is typically performed at a temperature of about 1000–1200° C. and then result in another stress relief of the structural polysilicon. The fabrication of the integrated circuit in this grown and polished epitaxial silicon will result in advanced MEMS such as Analog Devices' accelerometers and micro-gyroscopes.
The Analog Devices' Modular MEMS process shown at FIG. 1 is characterized by the following requirements:                a. The integrated circuit must be fabricated after the high surface topology mechanical parts. Since advanced integrated circuits involve very fine structures to be fabricated into a smooth substrate using short depth-of-focus photo equipment, a planar substrate with smooth surface finish is to be achieved following the micro-machining of these mechanical parts.        b. High-temperature stress-relief must be performed on the structural polysilicon after the MEMS fabrication, during the epitaxial growth of the substrate to be used for the integrated circuit portion.        c. It requires a CMP step after the epitaxial growth to achieve the required planarity and surface finish.        d. The integrated circuit must be fabricated after the CMP in the polished epitaxial silicon regions.        
Analog Devices' Modular MEMS process requires the use of a high-temperature stress-relief step of the MEMS structures during the epitaxial growth of the substrate to be used for the integrated circuit portion. This in turn imposes the use of CMP and the fabrication of the integrated circuit after fabrication of the mechanical parts.
SAIT's MEMS Process
A second example of such a restrictive high-temperature stress-relief process is Samsung Advanced Institute of Technology's (SAIT's) MEMS process involving the integration of a double polysilicon MEMS device with a standard integrated circuit. An example of this process is shown in the following reference: Y B Gianchandani, H Kim, M Shinn, B Ha, B Lee, K Najafi and C Song, “A fabrication process for integrating polysilicon microstructures with post-processed CMOS circuits”, J. Micromech. Microeng. 10 (2000) 380–386. This reference shows that SAIT's MEMS process uses a trench created using KOH to recess the microstructural polysilicon of the mechanical parts protected by an oxide/nitride cap layer during the fabrication of the integrated circuit AFTER the fabrication of the mechanical parts. The 1200° C. and 16 hours drive-in diffusion of the p-well implant is used as stress-relief of the microstructural polysilicon as to achieve advanced MEMS. SAIT's MEMS process is shown in FIG. 2 and comprises the following steps:                a. Create trench using KOH and a thermal oxide mask, deposit bottom oxide and nitride insulation layers, deposit and pattern first polysilicon layer.        b. Deposit and pattern first sacrificial oxide layer, deposit and pattern microstructural (second) polysilicon layer. In both of these steps the films are stripped from the CMOS circuit region before patterning the layers at the bottom of the trench.        c. Deposit and pattern second sacrificial oxide, deposit and pattern third polysilicon layer.        d. Strip the nitride from unrecessed regions and pattern the top cap layer protecting the MEMS parts. Perform the complete CMOS process until the metal interconnect layer. The p-well implant followed by a drive-in diffusion performed at 1200° C. for 16 h in an ambient of nitrogen and oxygen ensures stress relieving of the microstructural polysilicon.        e. Open contact holes in the MEMS regions, deposit and pattern aluminum for circuit interconnect and lead transfers between circuit and MEMS regions.        f. Cover aluminum metallization with a protective layer, remove protective cap layer from the MEMS regions, etch all sacrificial layers in BHF, remove protective layer from CMOS regions.        
The SAIT process shown in FIG. 2 is then characterized by the following requirements:                a. It also requires the integrated circuit to be fabricated after the high surface topology mechanical parts. This integrated circuit is fabricated at least 100 μm away from the recessed region where the mechanical parts are located. All layers constituting the integrated circuit are removed from the recessed region using the protective oxide/nitride cap layer as etch-stop and protection of the mechanical parts. Keeping the integrated circuit in the planar region of the silicon wafer and away from the recessed region eliminates the depth-of-focus problem.        b. It also requires a high-temperature stress-relief of the structural polysilicon. This is performed at 1200° C. for 16 hours during the drive-in diffusion of the p-well implant after the MEMS fabrication.        c. It does not require a CMP to achieve the required planarity and surface finish because the integrated circuit is fabricated at least 100 μm away from the recessed region where the mechanical parts are located and because the interconnections between the integrated circuit and mechanical parts are performed over the sloped region achieved by the KOH etch.        d. It requires the integrated circuit to be fabricated after the mechanical parts, into the horizontal regions, away from the recessed region where the mechanical parts are located.        
SAIT's MEMS process also imposes the use of a high-temperature stress-relief of the MEMS structures at 1200° C. for 16 hours during the drive-in diffusion of the p-well implant of the integrated circuit and imposes the fabrication of the integrated circuit AFTER the mechanical parts.
Sandia's IMEMS Process:
A third example of such a restrictive high-temperature stress-relief process is Sandia National Laboratories' (Sandia's) Integrated MicroElectroMechanical Systems (IMEMS) process involving the integration of a MEMS device incorporating at least two levels of polysilicon with an integrated circuit. An example of this process is shown in the following reference: J. H. Smith, S. Montague, J. J. Sniegowski, J. R. Murray, and P. J. McWhorter, “Embedded micromechanical devices for the monolithic integration of MEMS with CMOS”, IEDM 1995 proceedings, pp. 609–612. This reference shows that Sandia's MEMS process uses a trench created using KOH to recess the mechanical parts in a shallow trench, requires polishing the wafer using CMP, and requires sealing the mechanical parts in the trench using a silicon nitride layer. A high-temperature stress-relief is performed after the mechanical parts are embedded in the trench prior to processing conventional CMOS, bipolar or BiCMOS processes. This high-temperature stress-relief of the micro-structural polysilicon ensures that the subsequent thermal budget of the CMOS, bipolar or BiCMOS processing will not affect the mechanical properties of the polysilicon and will achieve an operational IMEMS. Sandia's IMEMS process shown at FIG. 3 is then characterized by the following:                a. It requires the CMOS bipolar or BiCMOS devices to be fabricated after the high surface topology mechanical parts. Again, since advanced integrated circuits involve very fine structures to be fabricated into a smooth substrate using short depth-of-focus photo equipment, a planar substrate with smooth surface finish is to be achieved following the micro-machining of these mechanical parts;        b. It requires a high-temperature stress-relief of the structural polysilicon. This is performed after the MEMS fabrication and prior the CMOS bipolar or BiCMOS processing;        c. It requires a CMP to be performed after the MEMS fabrication and prior the CMOS bipolar or BiCMOS processing;        d. It requires the CMOS bipolar or BiCMOS to be performed after the CMP into the polished silicon regions.        
The Sandia's IMEMS process also imposes the use of a high-temperature stress-relief of the MEMS structures prior the integrated circuit processing, imposes the use of CMP and imposes the fabrication of the integrated circuit after the mechanical parts.
MEMSCAP's PolyMUMPs Process:
A fourth example of such a restrictive process is MEMSCAP's Polysilicon Multi-User MEMS process, MUMP, of the following reference: David A. Koester, Allen Cowen, Ramaswamy Mahadevan and Busbee Hardy, “PolyMUMPs design handbook, revision 8.0”, 2002. This surface micromachining process uses three high-temperature stress-relieves of phosphorus-doped polysilicon, namely:                a. A high-temperature stress-relief of a 0.5 μm thick Poly 0 while diffusing the phosphorus atoms of a 2.0 μm thick phosphosilicate layer at 1050° C. for 1 hour in argon;        b. A high-temperature stress-relief of a 2.0 μm thick Poly 1 while diffusing the phosphorus atoms of a 0.2 μm thick phosphosilicate layer at 1050° C. for 1 hour in argon;        c. A high-temperature stress-relief of a 1.5 μm thick Poly 2 while diffusing the phosphorus atoms of a 0.2 μm thick phosphosilicate layer at 1050° C. for 1 hour in argon.        
MEMSCAP's MUMPs process shown in FIG. 4 is then characterized by the following:                a. It requires three 1050° C. 1 hour each high-temperature stress-relieves to dope and stress-relieve the three layers of polysilicon;        b. Because of these three successive 1050° C. 1 hour each dopant diffusions and stress-relieves, any tentative of integrating an integrated circuit to the MUMPs process would require the integrated circuit to be fabricated AFTER the MUMPs as to prevent the destruction of the junctions during such restrictive stress-relief steps.        
Robert Bosch GmbH's Surface Micromachining Process
A fifth example of such a restrictive high-temperature stress-relief process is Robert Bosch GmbH's surface micromachining process described in the following three references: Horst Mjinzel, Michael Offenberg, Klaus Heyers, Bernhard Elsner, Markus Lutz, Helmut Skapa, Heinz-Georg Vossenberg, Nicholas Buchan, Eckhard Graf, U.S. Pat. No. 5,937,275, “Method fof producing acceleration sensors”, Robert Bosch GmbH, filed on Jul. 9, 1996 and granted on Aug. 10, 1999; M. Furtsch, M. Offenberg, H. Muenzel, J. R. Morante, ‘Comprehensive study of processing parameters influencing the stress and stress gradient of thick polysilicon layers’, SPIE Conference Proceedings ‘Micromachining and microfabrication process technology III, conference proceedings’, SPIE Vol. 3223, pp. 130–141, Austin Tex., Sep. 29–30, 1997. http://www.europractice.bosch.com/en/download/customer_support.pdf
This process uses two levels of polysilicon, namely:                a. A first 0.45 μm thick surface polysilicon layer deposited at 630° C. by Low Pressure Chemical Vapor Deposition (LPCVD), implanted with antimony and annealed at 1000° C. in an oxygen ambient as to drive and activate the Sb dopant;        b. A second 10.3 μm thick structural epipoly layer is deposited as a 11.8 μm thick layer at a rate of 3.5 μm/minute and at a temperature of 1180° C. in a ASM Epsilon One Model-E2 single wafer epitaxy reactor using a trichlorosilane (SiHCl3), hydrogen (H2), and phosphine (PH3) process. The resulting 11.8 μm thick structural epipoly layer has a very rough surface (Ra of 260 nm) unacceptable for further processing and thus requiring the use of CMP to reduce the thickness of the structural epipoly layer to 10.3 μm and its surface roughness to about 5 nm.        c. Robert Bosch GmbH's surface micromachining process shown in FIG. 5 is then characterized by the following:        
It experiences two high-temperature stress-relief steps: A first, at 1000° C. in an oxygen ambient, to drive and activate the Sb dopant; and a second, at 1180° C., for the deposition of the structural epipoly layer;
Because of these two successive high-temperature stress-relief steps, any tentative of integrating an integrated circuit to Robert Bosch GmbH's surface micromachining process would also require the integrated circuit to be fabricated AFTER the MEMS process as to prevent the destruction of the junctions during such restrictive heat treatments.
Sandia's CMOS-First, Micromechanics-Last MEMS Process
A sixth example of such a restrictive high-temperature stress-relief process is reported by Sandia's CMOS-first, micromechanics-last MEMS process involving the integration of a MEMS device with an integrated circuit where conventional aluminium interconnects are completely replaced by tungsten interconnects to prevent melting the aluminium interconnects and allow the integrated circuit to withstand the 1100° C., 3 hours heat treatment required for the stress-relief of the micro-machined polysilicon. An example of this all-tungsten process is shown in the following three references: Stephen Montague, James H. Smith, Jeffrey. J. Sniegowski, Paul J. McWhorter, U.S. Pat. No. 5,798,283, “Method for integrating microelectromechanical devices with electronic circuitry”, Sandia National laboratories, filed on Sep. 6, 1995 and granted on Aug. 25, 1998; Carole C. Barron, James G. Flemming, Stephen Montague, U.S. Pat. No. 5,963,788, “Method for integrating microelectromechanical devices with electronic circuitry”, Sandia National laboratories, filed on Nov. 19, 1997 as continuation in-part of application Ser. No. 08/524,700 (U.S. Pat. No. 5,798,283) and granted on Oct. 5, 1999; James H. Smith, Stephen Montague, and Jeffrey. J. Sniegowski, “Material and processing issues for the monolithic integration of microelectronics with surface-micromachined polysilicon sensors and actuators”, Micromachining and Microfabrication '95, SPIE, October 1995.
These references show that Sandia's CMOS-first, micromechanics-last MEMS process of FIG. 6 fabricates the integrated circuit before the mechanical parts, thus reducing the surface topology and preventing the need for CMP. This is an improvement over the afore-mentioned Prior Art references but, following the integrated circuit fabrication, this process still requires a very restrictive 3 hours duration and 1100° C. stress-relief of the structural polysilicon. To enhance the thermal stability of the integrated circuit, aluminum interconnects are completely replaced by 1.0 μm thick low-stress tungsten interconnects deposited by chemical vapour deposition, CVD. In order to separate the tungsten from the underlying silicon at the contacts an adhesion layer/diffusion barrier stack of 15 nm of selective titanium silicide, TiSi, followed 50 nm of titanium nitride, TiN, is used. Where tungsten metallization is deposited over the field oxide, only the TiN layer is used. Since it is difficult to bond aluminium or gold bond wires to tungsten, bond pads are formed by using the structural polysilicon deposited on top of a 50 nm TiN diffusion barrier and the 1 micron of tungsten. The process is unstable because the compressive stress and surface roughness of the tungsten films are causing processing difficulties, such as delamination, or lifting, of the bondpads and photolithographically instabilities with projection steppers. A manually-aligned contact aligner has to be used; the TiN diffusion barrier sometimes fail during the 3 hours, 1100° C. stress-relief of the structural polysilicon, thus forming porous WTiSi and WSi at the basis of the contacts; and the out-diffusion of boron from the p+ source/drain implants in silicon causes a severe performance degradation of the p-channel devices due to an increase in contact resistance between tungsten and p-type silicon during the 3 hours, 1100° C. stress-relief of the structural polysilicon;
Because of the problems encountered in attempting to bring this technology to a manufacturing facility, Sandia decided to try other approaches besides the all-tungsten, CMOS-first, micromechanics-last MEMS process involving the required 3 hours duration and 1100° C. stress-relief of the structural polysilicon.
At this point, it is clear that the restrictive high-temperature stress-relief of the various upper-described popular MEMS processes prevents the integration of the integrated circuit BEFORE the micro-machining steps and prevents any type of modular integration of these micro-machining steps over the integrated circuit.
It is clear that any integration scenarios of these micro-machining steps over an integrated circuit require to stress-relief of structural silicon-based layers at a much lower temperature then 1000° C. The following will review the known techniques used to reduce the stress-relief temperature of deposited silicon films.
The techniques used to reduce the stress-relief temperature of deposited silicon films
University of Michigan's Low-Stress Polysilicon Process
A first example of a technique used to reduce the stress-relief temperature of un-doped silicon films is provided by the following publications from Universitry of Michigan: Khalil Najafi and Carlos. H. Mastrangelo, “Solid-state microsensors and smart structures”, 1993 IEEE Ultrasonics Symposium, pp. 341–350; Carlos. H. Mastrangelo and William C. Tang, “Surface-micromachined capacitive differential pressure sensor with lithographically defined silicon diaphragm”, Journal of microelectromechanical systems, Vol. 5, No. 2, June 1996; P.-C. Hsu, C. H. Mastrangelo, and K. D. Wise, “A high sensitivity polysilicon diaphragm condenser microphone”, 1998 MEMS Conference, Heidelberg, Germany, Jan. 25–29, 1998; B. P. Gogoi and C. H. Mastrangelo, “Force Balanced Micromachined Pressure Sensors”, IEEE Transactions on electron devices, IEEE Trans. Electron Dev., December 1999; B. P. Gogoi and C. H. Mastrangelo, “A low voltage force balanced pressure sensor with hermetically sealed servomechanism”, IEEE MEMS '99 Conference, pp. 493–498, Orlando, Fla., January 1999; Kun Wang and Clark T.-C. Nguyen, “High-Order Medium Frequency Micromechanical Electronic Filters”, Journal of microelectromechanical systems, Vol. 8, No. 4, December 1999; Robert D. White, Karl Grosh, “Design and characterization of a MEMS piezoresistive cochlear-like acoustic sensor”, Proceedings of IMECE'02, 2002 ASME International Mechanical Engineering Congress and Exposition, New Orleans, La., Nov. 17–22, 2002.
This technique describes the deposition of a low-stress un-doped polysilicon at a pressure of 160 mTorr and at a temperature of about 590–610° C. This un-doped polysilicon is electrically non-conductive and a phosphorus implantation at an energy of 100 keV and a dose of about 1–2E16/cm2 followed by an anneal at 950° C. for a few hours in nitrogen is required as to activate the phosphorus dopants and increase its electrical conductivity. This high-temperature stress-relief allow the mechanical stress of the electrically conductive polysilicon to be reduced to about 25 MPa but again limits the integration over an integrated circuit.
Alternatively, this technique describes the deposition of an un-doped polysilicon film at a temperature of 588° C. resulting in a non-conductive polysilicon having an as-deposited tensile stress of less then 100 MPa. Again, a phosphorus implantation at an energy of 50 keV and a dose of about 7E15/cm2, followed by a one hour duration 1050° C. phosphorus activation and stress-relief in nitrogen reduce its residual stress as much as possible.
This technique then requires a post-deposition implantation and a few hours duration 950° C. stress-relief and activation or a one hour duration 1050° C. stress-relief and actuation of the deposited polysilicon. The few hours duration 950° C. stress-relief and activation is marginally better then the one associated with the upper-described Prior Art references and, again, any tentative of an integrating integrated circuit to University of Michigan's surface micromachining process would also require the integrated circuit to be fabricated AFTER the MEMS process as to prevent the destruction of the junctions during such restrictive heat treatments.
UC Berkeley's Low-Stress Un-Doped Porous Polysilicon
A second example of a technique used to reduce the stress-relief temperature of silicon films is provided by the following publications from UC Berkeley: K. S. Lebouitz, A. Mazaheri, R. T. Howe, and A. P. Pisano, “Vacuum Encapsulation of Resonant Devices Using Permeable Polysilicon,” Proc. 12th International IEEE Conference on Micro Electro Mechanical Systems (MEMS '99), Orlando, Fla., pp. 470–5; Jeffrey D. Zahn, David Trebotich and Dorian Liepmann, “Microfabricated microdialysis microneedles for continuous medical monitoring”, 1st Annual International IEEE-EMBS Special Topic Conference on Microtechnologies in Medicine & Biology 1, Oct. 12–14, 2000, Lyon, France; John McCaslin Heck, “Polycrystalline silicon germanium for fabrication, release and packaging of microelectromechanical systems”, Ph. D. thesis, UC. Berkeley, Spring 2001; G. M. Dougherty, T. Sands, and A. Pisano, “The Materials Science of ‘Permeable Polysilicon’ Thin Films,” Symposium B: Materials Science of Microelectromechanical Systems (MEMS) Devices IV, MRS Fall 2001 Meeting, Boston, Mass., Nov. 27, 2001, Materials Research Society vol. 687; http://www-bsac.eecs.berkeley.edu\˜gmd\perm_page.html.
These publications show that an un-doped permeable polysilicon deposited at 597° C., 125 sccm SiH4, and 555 mTorr is characterized by a low residual stress due to pore defects (5–20 nm wide) between the polysilicon grains. This permeable polysilicon can also be deposited at 605° C., 250 sccm SiH4, and 550 mTorr. FIG. 7 shows the residual stress and surface structure of the un-doped permeable polysilicon. In order to use this low-stress un-doped permeable polysilicon as structural MEMS applications, it is again necessary to dope-and-activate it at a high-temperature ranging between 950° C. and 1050° C. as to activate the dopants and achieve low-stress conductive permeable polysilicon material. This described process to achieve doped permeable polysilicon would not be better then University of Michigan's surface micromachining process and would not substantially reduce the stress-relief temperature of the deposited conductive silicon material.
U. of Wisconsin's Low-Stress Re-Crystallized Polysilicon
A third example of a technique used to reduce the stress-relief temperature of un-doped silicon films is provided by the following publications from U. of Wisconsin: Henry Guckel and David W. Bums, U.S. Pat. No. 4,897,360, “Polysilicon thin film process”, Wisconsin Alumni Research Foundation, filed on Dec. 9, 1987 and granted on Jan. 30, 1990; Henry Guckel and Jeffry Sniegowski, U.S. Pat. No. 5,090,254, “Polysilicon resonating beam transducers”, Wisconsin Alumni Research Foundation, filed on Apr. 11, 1990 and granted on Feb. 25, 1992; Henry Guckel and Jeffry Sniegowski, U.S. Pat. No. 5,188,983, “Polysilicon resonating beam transducers and method of producing the same”, Wisconsin Alumni Research Foundation, filed on Jan. 3, 1992 and granted on Feb. 23, 1993.
These cited prior art patents protect a technique to form a low-stress un-doped re-crystallized silicon-based film. This film is deposited at a temperature of about 591° C. by low pressure chemical vapour deposition, LPCVD, using a 100% pure silane ambient at a pressure of about 300 mTorr resulting in a typical deposition rate of 6.8 nm/minute. The 2.0 μm thick as-deposited un-doped film shows two phases: A first phase, located between the substrate and the film interior, characterized by an un-doped polycrystalline material with 30 nm to 300 nm grains having no measurable preferred orientation, and a second phase, located above the first polycrystalline phase and extending up to the film surface, characterized by an un-doped amorphous material with a measured surface roughness of as low as 0.8 nm rms. The mechanical stress of this two-phase as-deposited un-doped film is typically 300 MPa compressive and can be converted to predetermined tensile stress levels by a re-crystallization using a post-deposition stress-relief in nitrogen during which the un-doped amorphous phase changes to the un-doped crystalline phase. A 60 minutes duration 835° C. stress-relief in nitrogen produces a single phase re-crystallized un-doped polycrystalline film having a final tensile stress of 130 MPa and no measurable increase in surface roughness. A lower stress-relief temperature results in a re-crystallized un-doped film with a tensile stress of as low as 20 MPa. These low mechanical stress re-crystallized un-doped films are yet non-conductive. Post-deposition doping of these un-doped re-crystallized films still requires diffusion and activation at a high-temperature incompatible with a potential underlying aluminum-based integrated circuit.
Siemens Aktiengesellschaft's Low-Stress Layered Polysilicon Structures
A fourth example of a technique used to reduce the stress-relief temperature of silicon films is provided by the following publications from Siemens Aktiengesellschaft: Markus Biebl, U.S. Pat. No. 5,753,134, “Method for producing a layer with reduced mechanical stresses”, Siemens Aktiengesellschaft, filed on Nov. 23, 1994 and granted on May 19, 1998.
This cited prior art patent protects a technique to form an un-doped silicon-based laminated structure having a reduced mechanical stress. As shown in FIG. 8, this low-stress un-doped laminated structure 30 could be deposited (respectively in order, from the underlying sacrificial layer to the top surface) using a first high-temperature compressive stress un-doped polysilicon 23, a first 0.1 to 3 nm thick auxiliary SiO2 layer 24 (produced, for example, by a waiting time at atmosphere), a second low-temperature tensile stress un-doped amorphous silicon 25, a second 0.1 to 3 nm thick auxiliary SiO2 layer 26, a third high-temperature compressive stress un-doped polysilicon 27, a third 0.1 to 3 nm thick auxiliary SiO2 layer 28 and a fourth low-temperature tensile stress amorphous un-doped silicon 29. The auxiliary SiO2 layers 24, 26, 28 assure that no epitaxial growth occurs when growing the un-doped amorphous silicon over the un-doped polysilicon.
This cited prior art patent discloses that the un-doped layers 23, 25, 27, 29, of individual thickness ranging between 50 nm and 1 μm, have to be implanted and high-temperature activated using rapid thermal activation, RTA, at approximately 1000° C. after the deposition of the corresponding layers as to reduce the electrical resistance of the laminated structure 30. Following these four RTA, the second amorphous un-doped silicon layer 25 and the fourth amorphous un-doped silicon layer 29 are converted into doped polycrystalline silicon, similar to doped polysilicon layers 23 and 27. To ensure that the laminated structure 30 has a sheet resistance corresponding to a single doped polysilicon layer having the same thickness, these four implantations and four high-temperature RTA steps should break up the auxiliary SiO2 layers 24, 26, 28. Again, the required four RTA steps at a temperature of about 1000° C. is too restrictive and do not allow MEMS integration AFTER the integrated circuit.
Case Western Reserve University's Low-Stress Layered Polysilicon Structures
A fifth example of a technique used to reduce the stress-relief temperature of silicon films is provided by the following publications from Case Western Reserve University: Arthur H. Heuer, Harold Kahn and Jie Yang, U.S. Pat. No. 6,268,068, “Low stress polysilicon film and method for producing same”, Case Western Reserve University, filed on Mar. 1, 1999 and granted on Jul. 31, 2001; Arthur H. Heuer, Harold Kahn and Jie Yang, U.S. Pat. No. 6,465,045, “Low stress polysilicon film and method for producing same”, Case Western Reserve University, filed on Oct. 18, 2000 and granted on Oct. 15, 2002; Arthur H. Heuer, Harold Kahn, Jie Yang and Stephen M. Phillips, U.S. Pat. No. 6,479,166, “Large area polysilicon films with predetermined stress characteristics and method for producing same”, Case Western Reserve University, filed on May 1, 2000 and granted on Nov. 12, 2002; Jie Yang, Harold Kahn, An-Qiang He, Stephen M. Phillips and Arthur H. Heuer, “A new technique for producing large-area as-deposited zero-stress LPCVD polysilicon films: The multipoly process”, IEEE Journal of microelectromechanical systems, Vol. 9, No. 4, December 2000, pp. 485–494.
These three cited prior art patents and this publication describe a technique similar to the upper-cited Siemens Aktiengesellschaft's patent resulting in the fabrication of low-stress laminated structures involving sequential combinations of low-temperature (570° C. or lower) tensile stress amorphous (or devitrified) un-doped silicon layers and of high-temperature (615° C.) compressive stress un-doped polysilicon layers. In this case, though, the SiO2 auxiliary layers are not used as to prevent the interaction of upper amorphous (or devitrified) un-doped layers with underlying un-doped polysilicon layers. In fact, this cited prior-art technique integrates all layers in a single deposition run, without atmospheric exposure.
As seen in FIG. 9, an example of such low-stress laminated structure combining tensile stress (about +200 MPa) un-doped amorphous silicon layers and compressive stress (about −200 MPa) un-doped polysilicon layers is a 3.0 μm thick laminated structure having an overall tensile mechanical stress of only 7 MPa using the following nine (9) layers:                a. A 59 minutes deposition of a devitrified un-doped polysilicon layer at 570° C. followed by a 25 minutes heating to reach 615° C.;        b. A 54 minutes deposition of a columnar un-doped polysilicon layer at 615° C. followed by a 30 minutes cooling to 570° C.;        c. A 118 minutes deposition of a devitrified un-doped polysilicon layer at 570° C. followed by a 25 minutes heating to reach 615° C.;        d. A 54 minutes deposition of a columnar un-doped polysilicon layer at 615° C. followed by a 30 minutes cooling to 570° C.;        e. A 118 minutes deposition of a devitrified un-doped polysilicon layer at 570° C. followed by a 25 minutes heating to reach 615° C.;        f. A 54 minutes deposition of a columnar un-doped polysilicon layer at 615° C. followed by a 30 minutes cooling to 570° C.;        g. A 118 minutes deposition of a devitrified un-doped polysilicon layer at 570° C. followed by a 25 minutes heating to reach 615° C.;        h. A 54 minutes deposition of a columnar un-doped polysilicon layer at 615° C. followed by a 30 minutes cooling to 570° C.;        i. A 59 minutes deposition of a devitrified un-doped polysilicon layer at 570° C.        
This cited prior art patent indicates that the 59 minutes duration deposition of the first and ninth un-doped layers (one-half the deposition time for each of un-doped layers 3, 5, and 7) provides a low residual stress and a relatively smooth outer finish. Again, the laminated structure of this cited prior art patent has to be implanted and high-temperature activated using either RTA or furnace activation at approximately 1000° C. and for a duration sufficiently long as to uniformly dope and reduce the electrical resistance of the obtained 3 μm thick laminated structure. Following this high-temperature dopant activation, the first, third, fifth, seventh and ninth devitrified un-doped silicon layers will be converted into doped polycrystalline silicon, similar to the second, fourth, sixth and eight doped polysilicon layers. This required RTA or furnace activation at a temperature of about 1000° C. is again too restrictive and do not allow MEMS integration AFTER the integrated circuit.
UC Berkeley's Low-Stress Re-Crystallized In-Situ Doped Polysilicon
A sixth example of a technique used to reduce the stress-relief temperature of silicon films is provided by the following publications from UC Berkeley: James M. Bustillo, Roger T. Howe and Richard S. Muller, “Surface Micromachining for Microelectromechanical Systems”, Proceedings of the IEEE, Vol. 86, No. 8, August 1998; Jocelyn Tsekan Nee, “Hybrid surface-/bulk micromachining processes for scanning micro-optical components”, Ph.D. thesis, UC Berkeley, Fall 2001.
A low-stress re-crystallized in-situ doped polysilicon has been investigated at UC Berkeley. By using a deposition temperature of 585–590° C., an in-situ doped low-resistivity polysilicon can be deposited at a relatively rapid rate. As shown in FIG. 10, this as-deposited low-resistivity phosphorus-doped polysilicon obtained at such 585–590° C. temperature suffers from crystallographic inhomogeneity observed as polysilicon grains near the underlying oxide interface which progressively disappear toward the upper surface. This non-homogeneous crystalline structure results in a stress gradient and requires a short duration 950° C. rapid-thermal annealing (RTA) to be performed as to achieve a low tensile stress with negligible stress gradient throughout the film thickness. Because the short duration 950° C. RTA replaces typically longer duration and higher temperature furnace anneals, this technique is slightly better then the upper-discussed techniques but still have a thermal budget which makes the MEMS AFTER the integrated circuit approach unfeasible because the interconnect materials will not resist such a high-temperature stress-relief.
Summary of the Restrictive High-Temperature Stress-Relief Processes Associated with the Cited Prior Art
The processes described in the upper prior art documents cannot allow the fabrication of advanced MEMS devices after the integrated circuit because of their excessive high-temperature stress-relief.
Analog Devices' Modular MEMS process requires the CMOS devices to be fabricated in a thick polished (using CMP) selective epitaxial silicon layer AFTER the mechanical parts are fabricated. In that case, the epitaxial silicon deposition at a temperature of about 1000–1200° C. and the well diffusions of the integrated circuit allow the stress relief of the structural polysilicon.
Samsung Advanced Institute of Technology's MEMS process also requires the CMOS devices to be fabricated after the mechanical parts. In this case, the 16 hours duration 1200° C. drive-in diffusion of the p-well implant of the integrated circuit is used as stress-relief of the microstructural polysilicon.
Sandia National Laboratories' IMEMS process also requires the CMOS, bipolar or BiCMOS devices to be fabricated after the mechanical parts. Again, a high-temperature stress-relief at temperatures of the order of 1000° C. is performed after the mechanical parts prior fabricating the integrated circuit as to ensure that the subsequent thermal budget required integrated circuit processing will not affect the mechanical properties of the mechanical parts.
MEMSCAP's Polysilicon Multi-User MEMS (PolyMUMPs) process requires three successive (1 hour each) 1050° C. exposures to dope and stress-relief the three layers of polysilicon doped by the phosphorus diffusing from the neighboring phosphosilicate layers. Again, any tentative of integrating CMOS devices to the MUMPs process would require the integrated circuit to be fabricated after the mechanical parts as to prevent the destruction of the junctions during these three 1050° C. exposures.
Robert Bosch GmbH's surface micromachining process requires two high-temperature exposures: A first one, at 1000° C. in an oxygen ambient, to drive and activate the Sb dopant of a first polysilicon layer; and a second one, at about 1100° C., for the deposition of the second structural epipoly layer. Again, this process requires the integrated circuit to be fabricated after the mechanical parts as to prevent the destruction of the junctions during such restrictive heat treatments.
Sandia National Laboratories' CMOS-first, micromechanics-last MEMS process decribes the fabrication the CMOS devices before the mechanical parts but still requires a very restrictive 3 hours duration and 1100° C. stress-relief of the structural polysilicon following the integrated circuit fabrication. To enhance the thermal stability of the integrated circuit, aluminum interconnects are completely replaced by 1.0 μm thick low-stress tungsten interconnects deposited by chemical vapor deposition, CVD over a titanium nitride, TiN, barrier layer. The process is yet unstable because of various issues related to: tungsten delamination and lifting at bond pads, tungsten surface roughness imposing manual photolithography, TiN barrier layer failure during the 3 hours, 1100° C. stress-relieve and boron out-diffusion during the 3 hours, 1100° C. stress-relief. These limitations caused Sandia to drop this idea and look for other approaches besides the all-tungsten, CMOS-first, micromechanics-last MEMS process.
University of Michigan's process describes the deposition of a low-stress un-doped polysilicon at a temperature of about 588–610° C. followed by the diffusion and activation at 950° C.–1050° C. (for one to a few hours in nitrogen) of a phosphorus implantation at an energy of 50 keV–100 keV and a dose of about 7E15/cm2–2E16/cm2 as to increase the electrical conductivity of the deposited polysilicon and reduce its mechanical stress to about 25 MPa. Again, the required 950° C.–1050° C. diffusion and activation of the phosphorus implantation again forces the integrated circuit to be fabricated AFTER the MEMS process as to prevent the destruction of the junctions during such restrictive heat treatments.
UC Berkeley's low-stress un-doped porous polysilicon process describes an un-doped low residual stress porous polysilicon deposited at 597° C.–605° C. under special conditions which requires its doping and activation at a high-temperature ranging between 950° C. and 1050° C. as to achieve low-stress conductive permeable polysilicon material. Again, the required 950° C.–1050° C. diffusion and activation of the low residual stress porous polysilicon again forces the integrated circuit to be fabricated AFTER the MEMS process as to prevent the destruction of the junctions during such restrictive heat treatments.
U. of Wisconsin's low-stress re-crystallized polysilicon process describes the 591° C. deposition of a 2.0 μm thick 300 MPa compressive stress un-doped silicon film having two phases: A bottom un-doped polycrystalline phase and an upper un-doped amorphous phase. A post-deposition stress relief at a temperature below 835° C. allows this film to be converted to a re-crystallized un-doped film with a tensile stress of as low as 20 MPa. The post-deposition diffusion and activation of these un-doped re-crystallized films at a temperature between 950° C.–1050° C. again forces the integrated circuit to be fabricated after the MEMS process as to prevent the destruction of the junctions during such restrictive heat treatments.
Siemens Aktiengesellschaft's low-stress layered polysilicon process describes a technique to form an low mechanical stress un-doped silicon-based laminated structure using a first high-temperature compressive stress un-doped polysilicon, a first auxiliary SiO2 layer, a second low-temperature tensile stress un-doped amorphous silicon, a second auxiliary SiO2 layer, a third high-temperature compressive stress un-doped polysilicon, a third auxiliary SiO2 layer and a fourth low-temperature tensile stress amorphous un-doped silicon. Again, post-deposition diffusions and activations of these laminated un-doped layers by four independent rapid thermal activations, RTA, at approximately 1000° C. again force the integrated circuit to be fabricated AFTER the MEMS process as to prevent the destruction of the junctions during such restrictive heat treatments.
Case Western Reserve University's low-stress layered polysilicon process describes the fabrication of a 3.0 μm thick low tensile stress (+7 MPa) laminated structures involving the sequential combination of five low-temperature (570° C. or lower) +200 MPa tensile stress amorphous (or devitrified) un-doped silicon layers and of four high-temperature (615° C.) −200 MPa compressive stress un-doped polysilicon layers with no auxiliary SiO2 layers in a single deposition run, without atmospheric exposure. Again, the post-deposition diffusion and activation of this un-doped laminated structure by RTA or furnace activation at approximately 1000° C. for a duration sufficiently long as to uniformly dope and reduce the electrical resistance of the obtained 3 μm thick laminated structure again forces the integrated circuit to be fabricated AFTER the MEMS process as to prevent the destruction of the junctions during such restrictive heat treatments.
UC Berkeley's low-stress re-crystallized in-situ doped polysilicon process describes a low-stress re-crystallized in-situ doped polysilicon deposited at a temperature of about 585–590° C. at a relatively rapid rate providing a film with a crystallographic inhomogeneity observed as polysilicon grains near the underlying oxide interface which progressively disappear toward the upper surface. This non-homogeneous crystalline structure results in a stress gradient and requires a short duration 950° C. RTA to achieve a low tensile stress with negligible stress gradient throughout the film thickness. Again, the short 950° C. RTA of the non-homogeneous crystalline structure forces the integrated circuit to be fabricated after the MEMS process as to prevent the destruction of the junctions and the interconnects during such restrictive heat treatments.
None of the cited prior art references described a process which can allow the effective fabrication of advanced MEMS devices after the integrated circuit because to each of these are associated an excessive high-temperature treatment to stress-relief, dope or activate the dopants of the deposited silicon.